发明名称 |
Mechanism for an efficient DLL training protocol during a frequency change |
摘要 |
An efficient delay locked loop (DLL) training protocol during a frequency change includes an integrated circuit with a memory physical layer (PHY) unit that includes a master DLL and a slave DLL. The master DLL may delay a first reference clock by an amount, and provide a reference delay value corresponding to the delay amount. The slave DLL may delay a second reference clock by a second amount based upon a received configuration delay value. An interface unit may generate the configuration delay value based upon the reference delay value. A power management unit may provide an indication that the frequency of the second reference clock is changing. In response to receiving the indication, the interface unit may generate a new configuration delay value that corresponds to the new frequency using a predetermined scaling value and provide the new configuration delay value to the memory PHY unit. |
申请公布号 |
US8645743(B2) |
申请公布日期 |
2014.02.04 |
申请号 |
US20100951788 |
申请日期 |
2010.11.22 |
申请人 |
MACHNICKI ERIK P.;CHEN HAO;MANSINGH SANJAY;APPLE INC. |
发明人 |
MACHNICKI ERIK P.;CHEN HAO;MANSINGH SANJAY |
分类号 |
G06F1/00 |
主分类号 |
G06F1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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