| 摘要 |
The present invention relates to a delay locked loop circuit of a semiconductor device and a driving method thereof including: a coarse delay line for delaying and outputting an input clock; a fine delay line for delaying an output of the coarse delay line and outputting an output clock; a replica delay unit for delaying the output clock as much as a predicted modeled value and outputting a feedback clock; a phase detection unit for generating a first phase detection signal by comparing a reference clock which is synchronized with the input clock and a phase of the feedback clock, generating a second phase detection signal by comparing the reference clock and a phase of a feedback clock which is as slow as a coarse unit delay and generating a third phase detection signal by comparing the reference clock and a phase of the feedback clock which is as fast as the coarse unit delay; a locking detection unit for selecting one between a first locking detection signal which is generated by comparing the previous state and current state of the second phase detection signal and a second locking detection signal which is generated by corresponding to a logic level at the same time as the first to third phase detection signals, and outputting the selection as the locking signal; and a control unit for controlling the coarse and fine delay lines by receiving the locking signal and the first phase detection signal. [Reference numerals] (222) First locking detector; (224) Second locking detector; (226) Generating a locking selection signal |
