发明名称 |
BIT ERROR TESTING AND TRAINING IN DOUBLE DATA RATE (DDR) MEMORY SYSTEM |
摘要 |
DDR PHY interface bit error testing and training is provided for Double Data Rate memory systems. An integrated circuit comprises a bit error test (BERT) controller that provides a bit pattern; and a physical interface having a plurality of byte lanes. A first byte lane is connected by a loopback path to a second byte lane and the BERT controller writes the bit pattern that is obtained using the loopback path to evaluate the physical interface. The evaluation comprises (i) a verification that the bit pattern was properly written and read; (ii) a gate training process to position an internal gate signal; (iii) a read leveling training process to position both edges of a strobe signal; and/or (iv) a write bit de-skew training process to align a plurality of bits within a given byte lane. |
申请公布号 |
US2014029364(A1) |
申请公布日期 |
2014.01.30 |
申请号 |
US201213559741 |
申请日期 |
2012.07.27 |
申请人 |
BHAKTA DHARMESH N.;BUTT DERRICK;WEBSTER CURTIS M.;LSI CORPORATION |
发明人 |
BHAKTA DHARMESH N.;BUTT DERRICK;WEBSTER CURTIS M. |
分类号 |
G11C29/00 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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