发明名称
摘要 Methods and systems mitigate a soft error in an integrated circuit. A map is stored in a memory, and the map specifies a criticality class for each storage bit in the integrated circuit. A mitigative technique is associated with each criticality class. The soft error is detected in a corrupted one of the storage bits. The mitigative technique is performed that is associated with the criticality class specified in the map for the corrupted storage bit.
申请公布号 JP2014502452(A) 申请公布日期 2014.01.30
申请号 JP20130538733 申请日期 2011.10.10
申请人 发明人
分类号 H03K19/177;G06F11/10;G06F12/16;H03K19/003 主分类号 H03K19/177
代理机构 代理人
主权项
地址