发明名称 Integrated Circuit Interconnects and Methods of Making Same
摘要 A copper alloy layer is blanket deposited over a low k dielectric layer and in via openings within the low k dielectric layer. The blanket deposited layer is then anisotropically etch to form horizontal interconnects. The interconnects are annealed to form a metal oxide barrier lining. A second low k dielectric layer is then depositing over the horizontal interconnects. Air gaps can be formed between adjacent interconnects to lower parasitic capacitance therebetween.
申请公布号 US2014027908(A1) 申请公布日期 2014.01.30
申请号 US201213559107 申请日期 2012.07.26
申请人 TSAI CHENG-HSIUNG;LEE CHUNG-JU;TSAI TSUNG-JUNG;LEE HSIANG-HUAN;LEE MING HAN;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 TSAI CHENG-HSIUNG;LEE CHUNG-JU;TSAI TSUNG-JUNG;LEE HSIANG-HUAN;LEE MING HAN
分类号 H01L21/768;H01L23/535 主分类号 H01L21/768
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