| 摘要 |
PROBLEM TO BE SOLVED: To provide a solid-state imaging device capable of tuning multiple locations for the number of lines or the number of rows of a pixel array part, or the corresponding multiple-lines or multiple-rows of the pixel array, without difficulty in proof pressure occurred with an SOC structure and other processes.SOLUTION: A repeated array pattern circuit 31 is formed on a first chip 32, an adjustment circuit 33 is formed on a second chip 34, and the first chip 33 and the second chip 34 are electrically interconnected via a connection part 35 to achieve a three-dimensional connection. Thus, it will be possible to tune multiple locations for the number of lines or the number of rows of a pixel array part, or the corresponding multiple-lines or multiple-rows of the pixel array, without restriction on the number of terminals (pins) for connecting the repeated array pattern circuit 31 and the adjustment circuit 33. |
