发明名称 |
CIRCUIT FOR REDUCING NEGATIVE BIAS TEMPERATURE INSTABILITY |
摘要 |
A control circuit comprises a first NOR gate, a first NMOS transistor, and a first PMOS transistor. The control circuit also comprises an output node. The control circuit further comprises a half latch keeper circuit coupled to a gate of the first NMOS transistor and to a gate of the first PMOS transistor. The half latch keeper circuit is configured to keep the output node at a logical 1 during a standby mode. The control circuit additionally comprises an operational PMOS transistor coupled to the output node. An output of the first NOR gate is coupled to a gate of the operational PMOS transistor. The control circuit is configured to turn off the operational PMOS transistor during the standby mode. |
申请公布号 |
US2014028350(A1) |
申请公布日期 |
2014.01.30 |
申请号 |
US201314045364 |
申请日期 |
2013.10.03 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
CHERN CHAN-HONG;HSUEH FU-LUNG;HUANG MING-CHIEH;SHEFFIELD BRYAN;LIN CHIH-CHANG |
分类号 |
H03K19/0185 |
主分类号 |
H03K19/0185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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