ON-DIE TERMINATION CIRCUIT, SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM

摘要

An ODT circuit is activated/deactivated in response to a latency control signal or a clock enable signal. The ODT circuit includes an ODT control circuit and an ODT section. The ODT control circuit determines an ODT status based on a read latency control signal (RL) and/or a write latency control signal (WL) to generate an ODT control signal. The ODT section is activated/deactivated in response to the ODT control signal.