| 摘要 |
On a surface of a Si substrate, a nonvolatile memory cell, an nMOS transistor (101n), and a pMOS transistor (101p) are formed, and thereafter an interlayer insulation film covering the nonvolatile memory cell, the nMOS transistor, and the pMOS transistor is formed. Next, in the interlayer insulation film, there are formed plural contact plugs connected respectively to a control gate (CG) of the nonvolatile memory cell, a source or a drain of the nMOS transistor, and a source or a drain of the pMOS transistor. Thereafter, there is formed a single-layer wiring (M1) connecting the control gate to the sources or drains of the nMOS transistor and the pMOS transistor via the plural contact plugs. |
