| 摘要 |
<p>A multiport memory comprises an array of storage cells for storing data. Each storage cell comprises data storage circuitry and a plurality of access control devices for isolating the storage circuitry from or connecting the storage circuitry to a data line. The memory comprises a plurality of sets of access control lines and corresponding data lines. The access control lines of each set controls one of the plurality of the access control devices for each of the storage cells. Each of the data lines is coupled to a column of the storage cells and each of the access control lines is coupled to a row of the storage cells. The multiport memory further includes access control circuitry configured to assign each data access port to one among the data access ports, the access control lines, and the sets of the data lines corresponding thereto. The access control circuitry comprises collision detection circuitry configured to detect a colliding data access request received from the second data access port that requests access to a row of the storage cells currently being accessed by a data access request received from the first data access port. The access control circuitry is configured to respond to the detected collision to assign the set of the access control lines and corresponding data lines currently assigned to the first data access port to the second data access port and, after the completion of the data access request received from the first data access port, to assign the first data access port to the set of the access control lines and corresponding data lines previously assigned to the second access port. [Reference numerals] (21) Array; (25) Access control circuit; (28,CC) Collision; (29) Indicator; (30) Processor A; (32) Processor B; (AA) Port A; (BB) Row comparator; (DD) Port B</p> |
