| 摘要 |
<p>The method involves encoding state 0 of a memory element in stable conditions A1 and B0, and encoding state 1 of the memory element in stable conditions A0 and B1 by measurement of an electrical variable e.g. voltage (V) and capacitance (CA), of a series circuit. The electrical variable is selected, where a memory cell (A) in the state A0/A1 carries out respective contributions than another memory cell (B) in the state B0/B1. Alternating voltage drop (Vmess) is measured over the memory element, where the memory element is designed as a layer of active material. An independent claim is also included for a memory element.</p> |
