Methods and systems for adjusting nvm cell bias conditions for program/erase operations to reduce performance degradation

摘要

Methods and systems are disclosed for adjusting program/erase bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems (102) having an NVM controller (212), a bias voltage generator (150), and an NVM cell array (204). Further, the NVM systems can store performance degradation information (130) and program/erase bias condition information (132) within storage circuitry. The disclosed embodiments adjust program/erase bias conditions for the NVM cells based upon performance degradation determinations, for example, temperature-based performance degradation determinations and interim verify based performance degradation determinations.