Computer architecture with a hardware accumulator reset

摘要

A processor is provided with multiple address generator circuits and a zero-overhead-loop circuit for processing multi-dimensional data arrays using multiple nested program loops. An event generated by the address generator circuits or by the zero-overhead-loop circuit is selected to produce one or more selected events. A reset signal is generated responsive to the selected event. Responsive to the reset signal, an accumulator within the processor is reset to zero or another initial value thus avoiding breaking pipelined execution of the processor.