| 摘要 |
1513893 Integrated circuits INTERNATIONAL BUSINESS MACHINES CORP 21 May 1975 [26 June 1974] 21875/75 Heading H1K The component logic circuits of a planar LSI chip are arranged in a rectangular array with a level of metallization, disposed above the array on a layer of insulating material, comprising (a) a plurality of mutally parallel conductive lines arranged in groups, each group being disposed above and extending parallel to a respective interface between adjacent rows of cell, and being selectively connected to some of the cells to provide interconnections between and voltage level supplies to the cells, and (b) clustered conductive patterns disposed above the cells between the groups to provide the internal connections of the cells. In a described arrangement in which each cell comprises a Schottky diode clamped TTL circuit, the cells are arranged in 4 x 2 blocks with spaces between adjacent rows and columns of blocks, each cell being a mirror image of the corresponding cells in the adjacent rows and columns. The groups of parallel lines are located over the spaces between adjacent rows. A second level of metallization is present on insulation overlying the first level, consisting of conductive lines normal to those of the first level providing further interconnections between the cells and cross-over connections between non-adjacent lines of the first level, while a third level constitutes a voltage distribution bus arrangement supplying the voltage level conductors in the lower levels. Generally conventional processing steps for production of the components of the LSI and the various levels of metallization and intervening insulation are described in detail. |
