发明名称 |
Refresh control circuit, memory apparatus and refresh control method using the same |
摘要 |
A memory apparatus is configured to generate refresh addresses with different values in response to one refresh command and an address, and perform a plurality of refresh operations with time differences in response to the refresh addresses. Herein, the refresh operations are performed within a refresh row cycle time. |
申请公布号 |
US8638629(B2) |
申请公布日期 |
2014.01.28 |
申请号 |
US201113181997 |
申请日期 |
2011.07.13 |
申请人 |
KIM SANG HUI;SEO JU YOUNG;SK HYNIX INC. |
发明人 |
KIM SANG HUI;SEO JU YOUNG |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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