发明名称 High speed interface for multi-level memory
摘要 A memory chip includes a plurality of storage elements. A method of controlling the memory chip includes receiving a plurality of target values from a memory controller. Each target value of the plurality of target values received from the memory controller corresponds to a respective one of the plurality of storage elements. The method further includes, for each storage element of the plurality of storage elements, adjusting a measurable parameter of the storage element until the measurable parameter of the storage element reaches the target value corresponding to the storage element received from the memory controller.
申请公布号 US8638619(B2) 申请公布日期 2014.01.28
申请号 US201313872729 申请日期 2013.04.29
申请人 MARVELL WORLD TRADE LTD. 发明人 SUTARDJA PANTAS
分类号 G11C7/00;G11C7/22 主分类号 G11C7/00
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