发明名称 |
Bit line charge accumulation sensing for resistive changing memory |
摘要 |
A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed. |
申请公布号 |
US8638597(B2) |
申请公布日期 |
2014.01.28 |
申请号 |
US201213476368 |
申请日期 |
2012.05.21 |
申请人 |
JUNG CHULMIN;LU YONG;KIM KANG YONG;KIM YOUNG PIL;SEAGATE TECHNOLOGY LLC |
发明人 |
JUNG CHULMIN;LU YONG;KIM KANG YONG;KIM YOUNG PIL |
分类号 |
G11C11/00 |
主分类号 |
G11C11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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