发明名称 |
Word line decoder circuit apparatus and method |
摘要 |
One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation. |
申请公布号 |
US8638636(B2) |
申请公布日期 |
2014.01.28 |
申请号 |
US20100816960 |
申请日期 |
2010.06.16 |
申请人 |
SHEN SHIN-JANG;WU BO-CHANG;YU CHUAN YING;CHEN KEN-HUI;CHANG KUEN-LONG;HUNG CHUN-HSIUNG;MACRONIX INTERNATIONAL CO., LTD. |
发明人 |
SHEN SHIN-JANG;WU BO-CHANG;YU CHUAN YING;CHEN KEN-HUI;CHANG KUEN-LONG;HUNG CHUN-HSIUNG |
分类号 |
G11C8/00 |
主分类号 |
G11C8/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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