发明名称 Semiconductor device having redundant bit line provided to replace defective bit line
摘要 Disclosed herein is a device that responds to mat selection information, which is used to select one of memory mats, and selects at least one defective address from a plurality of defective addresses which are stored, for example, in a fuse circuit. When the access address information is coincident with a selected defective address, a redundant memory cell is accessed for reading or writing data in place of a normal memory cell. In a refresh operation, on the other hand, a column addressing, including the above replacement of a normal memory cell with a redundant memory cell, is deactivated.
申请公布号 US8638625(B2) 申请公布日期 2014.01.28
申请号 US201213396985 申请日期 2012.02.15
申请人 RIHO YOSHIRO;MIZUKANE YOSHIO;NODA HIROMASA;ELPIDA MEMORY, INC. 发明人 RIHO YOSHIRO;MIZUKANE YOSHIO;NODA HIROMASA
分类号 G11C7/00 主分类号 G11C7/00
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