| 摘要 |
A shaper of single code group of pulses with programmable parameters comprises two reversible binary counters having clock input, a summing/subtraction mode setting input, a synchronous parallel load enable input and loading data input, a counting mode enable input; an asynchronous reset, an overflow output; a circuit comprising in series connected resistor and capacitor, synchronous D and JK-flip-flops with asynchronous reset, an inverter, first and second two-input elements AND, first and second elements OR. Third (two-input) and fourth (four-input) elements OR, a two-input AND-NOT element are introduced. |
