发明名称 WAFER LEVEL PACKAGE RESISTANCE MONITOR SCHEME
摘要 <p>An integrated circuit includes a monitoring circuit and a monitored circuit connected with the monitoring circuit. The monitoring circuit is operable to determine during fabrication if a resistance of a connection between an in-fab redistribution layer connector and a post-fab redistribution layer connector exceeds a threshold.</p>
申请公布号 KR101356406(B1) 申请公布日期 2014.01.27
申请号 KR20120107147 申请日期 2012.09.26
申请人 发明人
分类号 H01L21/66 主分类号 H01L21/66
代理机构 代理人
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