| 摘要 |
The present invention relates to a wafer test operation for a semiconductor memory device. The semiconductor memory device comprises: an operation signal generator for alternately activating a test operation signal and a normal operation signal whenever codes applied to a plurality of command pads have a set value in the section where a test enable signal is activated; a transmission selection unit for transmitting, through a normal command path, codes applied to the command pads in the activation section of the normal operation signal and transmitting, through a test command path, codes applied to the command pads in the activation section of the test operation signal; and an internal circuit for performing a normal test operation in response to codes transmitted through the normal command path and performing a test operation in response to codes transmitted through the test command path, in the section where the test enable signal is activated, and performing a normal operation in response to codes transmitted through the normal command path in the section where the test enable signal is inactivated. [Reference numerals] (100) Operation signal generator; (120) Transmission selection unit; (142) Normal decoding unit; (144) Test decoding unit; (146) Internal operation unit |
