发明名称 SKEW REDUCTION CIRCUIT
摘要 A circuit for skew reduction, includes: first signal lines configured to transmit first signals delayed by first paths respectively; second signal lines configured to transmit second signals delayed by second paths respectively; and a first swap circuit, wherein the first swap circuit is configured to swap and connect the at least one of the first signal lines to the at least one of the second signal lines, when a mutual delay time difference of the second signals in a state where the at least one of the first signal lines is swapped and connected to the at least one of the second signal lines is smaller than a mutual delay time difference of the second signal lines in a state where the first signal lines is connected to the second signal lines without being swapped.
申请公布号 US2014021998(A1) 申请公布日期 2014.01.23
申请号 US201313945476 申请日期 2013.07.18
申请人 FUJITSU SEMICONDUCTOR LIMITED 发明人 NEMOTO YUTAKA;OGAWA YOSHIMASA
分类号 H03K5/00 主分类号 H03K5/00
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