| 摘要 |
In one aspect of the present invention, a FFT circuit (1) includes a pipeline, using SDF architecture, in which L number of butterfly processing elements are connected. Each of LHF number of butterfly PEs (10) corresponding to a first stage to a LHFth stage is configured so that, taking N/(2S-1) pieces of output data as a unit starting from lead output data of which the Data Flow Graph (DFG) index (i) is "0", the order of output data is changed so that, with the N/(2S-1) pieces of output data, intermediate result data GS(i) having bS(i)=1 is output after intermediate result data GS(i) having bS(i)=0, where N is the number of FFT points, S is an integer expressing a stage number, and bS(i) means the Sth bit from the least significant bit when writing the DFG index (i) as binary. |
