发明名称 |
MEMORY SUBSYSTEM AND COMPUTER SYSTEM |
摘要 |
The present invention provides a computer system including a CPU and a memory subsystem connected via a system bus to communicate with each other. The computer system 100 includes a bus monitor 50 connected to the system bus 10 to monitor the frequency of access requests from the CPU 20 to the memory subsystem 30, and a latency changing means 60 for sending a control signal to the memory subsystem to change the latency of the access requests in response to the frequency of the access requests received from the bus monitor. |
申请公布号 |
US2014025855(A1) |
申请公布日期 |
2014.01.23 |
申请号 |
US201313945330 |
申请日期 |
2013.07.18 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
FUJITA NORIO;HORI MASAHIRO;MURAKAMI MASAHIRO;OKAZAWA JUNKA |
分类号 |
G06F13/16 |
主分类号 |
G06F13/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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