发明名称 |
APPARATUSES AND METHODS TO SUPPRESS POWER SUPPLY NOISE HARMONICS IN INTEGRATED CIRCUITS |
摘要 |
Apparatuses and methods for suppressing power supply noise harmonics are disclosed. A method includes selecting at least one flip-flop of a plurality of data paths of an integrated circuit based on a slack associated with the at least one flip-flop. The method also includes providing at least one delay circuit at an output of at least one flip-flop. The at least one delay circuit is configured to delay the output of the at least one flip-flop by a threshold clock cycle for managing current at a positive edge of a clock input and current at a negative edge of the clock input, thereby suppressing power supply noise harmonics of the integrated circuit. |
申请公布号 |
US2014021993(A1) |
申请公布日期 |
2014.01.23 |
申请号 |
US201213554762 |
申请日期 |
2012.07.20 |
申请人 |
PODDUTUR SUMANTH REDDY;NARAYANAN PRAKASH;SINGHAL VIVEK;TEXAS INSTRUMENTS INCORPORATED |
发明人 |
PODDUTUR SUMANTH REDDY;NARAYANAN PRAKASH;SINGHAL VIVEK |
分类号 |
H03K5/1252;G06F17/50 |
主分类号 |
H03K5/1252 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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