| 摘要 |
<p>A delay circuit has a delay gate group and a voting circuit. The delay gate group has three or more types of delay gates, which are configured by inverters of one stage or a plurality of stages having the same type of transistor, and which input an input signal and then output a delayed signal after a period of delay time, wherein each of the three or more types of delay gates are configured by inverters of different types of transistors, and the periods of the delay times of the three or more types of delay gates are set to be the same design delay time. The voting circuit inputs the delay signal of each delay gate of the delay gate group, and on the basis of the delay signals output from a majority of delay gates that have actual delay times that are equivalent to the design delay times among the delay gates of the delay gate group, outputs an output signal that has an actual delay time that is equivalent to the design delay time.</p> |
