发明名称 |
Digital Phase Locked Loop with Feedback Loops |
摘要 |
Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals. |
申请公布号 |
US2014021992(A1) |
申请公布日期 |
2014.01.23 |
申请号 |
US201313962325 |
申请日期 |
2013.08.08 |
申请人 |
BROADCOM CORPORATION |
发明人 |
FRANTZESKAKIS EMMANOUIL;SFIKAS GEORGIOS;WU STEPHEN;SRINIVASAN RADHA;JENSEN HENRIK THOLSTRUP;IBRAHIM BRIMA |
分类号 |
H03L7/08 |
主分类号 |
H03L7/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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