发明名称 Configurable thread ordering for a data processing apparatus
摘要 A data processing apparatus and method processing data are disclosed. Execution circuitry is configured to execute multiple threads to perform data processing on input data by reference to at least one coordinate value of points in a reference domain. Thread allocation circuitry is configured to specify a selected point in the reference domain for each thread of the multiple threads respectively in order to allocate the data processing by specifying for each thread the at least one coordinate value of the specified point for that thread. Each thread accesses the input data with reference to its selected point in the reference domain and an order in which points in the reference domain are allocated to threads for data processing is configurable in the thread allocation circuitry.
申请公布号 GB201321831(D0) 申请公布日期 2014.01.22
申请号 GB20130021831 申请日期 2013.12.10
申请人 ARM LIMITED 发明人
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