发明名称 TWO-DIMENSIONAL MATCHING CIRCUIT
摘要 PURPOSE:To perform the picture data processing at a high speed by attaining execution of a matching operation with a clock per picture element between the (mXm) multi-value picture data and a (nXn)-window pattern. CONSTITUTION:Arithmetic units PE11 and 55 equal to an arithmetic element PE(n=5) arrayed into a matrix of (5X5) and contain line buffers LB1-LB4 to give delays. The window data wij is applied to each of arithmetic elements PE11-PE55. A picture memory 10 is read out in a TV scan system to obtain the picture element data fij. This data fij is fetched to a latch 54 through an input buffer 52. The picture data f11-f51 equivalent to a line of a window are applied to arithmetic units PE41-PE45 through the buffer LB1 which gives a delay equivalent to (m-n) picture elements are then finally to arithmetic units PE11-PE15 through the buffer LB2 having the same delay as that of the buffer LB1. Thus each output of the sum of the difference absolute values obtained by giving a TV scan to the memory 10 through a window 12 is delivered sequentially in the 1-clock timing.
申请公布号 JPS6083181(A) 申请公布日期 1985.05.11
申请号 JP19830191972 申请日期 1983.10.14
申请人 FUJITSU KK 发明人 MASUI TAKESHI;SASAKI SHIGERU
分类号 G06T1/20;G06T5/20;G06T7/00 主分类号 G06T1/20
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