发明名称 DATA PROCESSOR
摘要 PURPOSE:To attain monitor for the state of plural input/output controllers included in a data processor without deteriorating the data transfer speed of the input/output controller nor the CPU efficiency, by adding a state monitor device in the data processor. CONSTITUTION:A state monitor device 13 always monitors the state of plural input/output controllers regardless of an instruction of a central processor (CPU) 11 through plural signal lines 14. When some or all of the input/output controllers 12 is confirmed by the CPU11, an input/output instruction is sent to the device 13 from the CPU11. Then the CPU11 receives data from the device 13 and can read the state of the input/output controllers 12. In other words, it is not needed for the CPU11 to send an instruction for detection of the state of each controller 12 just by receiving data from only the device 13. Furthermore the CPU11 has no need to send an instruction even through the controller 12 is delivering or receiving data.
申请公布号 JPS6083163(A) 申请公布日期 1985.05.11
申请号 JP19830190970 申请日期 1983.10.14
申请人 NIPPON DENKI KK 发明人 TANIGUCHI HIDENORI
分类号 G06F13/14;G06F13/12 主分类号 G06F13/14
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