| 摘要 |
Phase controllers 18 synchronise the channels (16) associated with respective multiple In-Phase and Quadrature (IQ) demodulators (12) according to a phase detector (20) and a system clock (24) located at different distances from the demodulators. The phase controllers 18 (eg. a Phase-Lock Loop PLL) regenerate the system signal 26 as a synchronised signal 28, one of which is selected as a reference phase signal (30), and the phase detector 20 then determines which of the output signals 28 are out of phase with the reference and sends a phase-adjusting control signal 32. The IQ demodulators then output phase-corrected real (34) and imaginary (36) components. |
