发明名称 |
Phase-locked loop (PLL) fail-over circuit technique and method to mitigate effects of single-event transients |
摘要 |
A PLL fail-over circuit technique and method to mitigate the effects of single-event transients comprises providing a pair of substantially identical phase-locked loops and producing a respective delayed clock signal from each. The outputs of the phase-locked loops are monitored for errors comprising high frequency transients or differences in clock signal outputs from a reference frequency. A clock out signal is output representative of the first delayed clock signal if an error is detected in the second phase-locked loop and the second delayed clock signal is output if an error is detected in the first phase-locked loop. |
申请公布号 |
US8633749(B2) |
申请公布日期 |
2014.01.21 |
申请号 |
US201213560774 |
申请日期 |
2012.07.27 |
申请人 |
BASS DEREK E.;PFEIL JOHN W.;AEROFLEX COLORADO SPRINGS INC. |
发明人 |
BASS DEREK E.;PFEIL JOHN W. |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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