| 摘要 |
<p>PURPOSE:To make a bus control circuit efficient while suppressing the reduction of the processing capacity of a sub-CPU by providing the circuit with a circuit for a main CPU to directly access a device managed by the sub-CPU and a circuit for arbitrating a bus using right managed by the sub-CPU. CONSTITUTION:The main CPU 1 accesses a main device 3 through a normal main bus 2 and the sub-CPU 4 accesses a sub-device 6 through a sub-bus 5. If the main CPU 1 tries to access the sub-device 6, a sub-device access request is outputted from a decoder 8 to an arbitrating circuit 9. The arbitrating circuit 9 forms timing by monitoring a sub-CPU bus status signal 10, a main CPU control signal 11 and a CPU control signal 12, synchronizing the access cycles of both the CPUs by using a READY signal, closes a sub-bus buffer 13, and opens a bus connecting buffer 14 so that the main CPU 1 directly accesses the sub-device 6.</p> |
