发明名称 DATA GENERATION CIRCUIT, SEMICONDUCTOR DEVICE AND DETERMINATION METHOD
摘要 PROBLEM TO BE SOLVED: To provide a determination circuit capable of confirming that an expected bit string is generated.SOLUTION: A data generation circuit includes: a latch circuit which has a set input and a reset input connected in common, and outputs a bit string when receiving an input signal, and which has a transistor in which a threshold is set by adjusting ion concentration, latches and outputs a first output state in response to an input signal in the case that drive voltage is voltage different from operation voltage, and latches and outputs a second output state based on a threshold set in response to the input signal in the case that the drive voltage is the operation voltage; and a determination circuit for receiving a bit string outputted by the latch circuit, comparing data of a first bit with data of a second and succeeding bits, and determining whether the data of the second and succeeding bits are coincident and whether the data of the second and succeeding bits is data obtained by inverting the data of the first bit, and generates output data on the basis of a determination result of the determination circuit.
申请公布号 JP2014010867(A) 申请公布日期 2014.01.20
申请号 JP20120147017 申请日期 2012.06.29
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 TAKASAKI YUMIKO;SUZUKI HIDEAKI
分类号 G11C29/42 主分类号 G11C29/42
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