发明名称 DELAY CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a delay circuit that implements a large time constant of an integration circuit when an input signal changes from an H level to an L level and an output of an input inverter changes to an H level, independently of increase in the area of a capacitance.SOLUTION: The delay circuit includes: an input inverter 12; an output inverter; the integration circuit having a resistance and the capacitance; and a charge/discharge control circuit 10 for controlling a time constant in which the integration circuit is charged/discharged. The charge/discharge control circuit 10 has a current mirror circuit 22 comprising a PMOS 13 and a PMOS 15 smaller in transistor size ratio than the former transistor. During a current mirror action of the two PMOSs, a lower current flows through the right PMOS 15 than through the left PMOS 13 in accordance with the transistor size ratio. A delay increases with increasing size ratio, and the capacitance can shrink by the increase to provide a smaller area for the original delay.
申请公布号 JP2014011677(A) 申请公布日期 2014.01.20
申请号 JP20120147663 申请日期 2012.06.29
申请人 SEIKO NPC CORP 发明人 SATO MASATOSHI;TEZUKA KAZUHITO
分类号 H03K5/13 主分类号 H03K5/13
代理机构 代理人
主权项
地址