SEMICONDUCTOR INTEGRATED CIRCUIT, AND DESIGN METHOD AND MANUFACTURING METHOD OF THE SAME

摘要

PROBLEM TO BE SOLVED: To provide: a semiconductor integrated circuit that minimizes a parasitic capacitance that is generated due to overhead of a conductive line, especially a gate line; and a design method and manufacturing method of the same.SOLUTION: A method of designing a semiconductor integrated circuit having a FinFET structure includes the steps of: performing pre-simulation of the semiconductor integrated circuit to be designed; designing the layout of components of the semiconductor integrated circuit that includes first and second element regions and a first conductive line that extends across the first and second element regions, on the basis of the pre-simulation; and changing a first disconnection region by at least one design rule, so as to minimize the overhead of the first conductive line that is generated by the first disconnection region that is arranged between the first element region and second element region and electrically disconnects the first conductive line.