发明名称 VERTICAL GATE DEVICE WITH REDUCED WORD LINE RESISTIVITY
摘要 <p>The present invention relates to a semiconductor device including a substrate including a main surface; a first conductive area; a second conductive area; a first pillar vertically extended on the main surface of the substrate and defining a channel area included between the first conductive area and the second conductive area; a first gate included on the upper part of the channel area of the first pillar; an embedded word line extended from the lower part of the first pillar in a first direction and supplying a first control signal to the first gate; and a first interposer connecting the first gate and the embedded word line in order for the first control signal to be applied to the first gate through the embedded word line.</p>
申请公布号 KR20140007241(A) 申请公布日期 2014.01.17
申请号 KR20120091799 申请日期 2012.08.22
申请人 SK HYNIX INC. 发明人 PARK, JIN CHUL
分类号 H01L29/78;H01L21/336 主分类号 H01L29/78
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