发明名称 DATA INTERFACE CLOCK GENERATION
摘要 In one embodiment, an apparatus may include a clock generator to generate a format clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the format clock signal and the serial data.
申请公布号 US2014015581(A1) 申请公布日期 2014.01.16
申请号 US201213545275 申请日期 2012.07.10
申请人 YANG WEI-LIEN 发明人 YANG WEI-LIEN
分类号 H03K3/017 主分类号 H03K3/017
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