| 摘要 |
A CAS latency circuit and a semiconductor memory device including the same are provided to generate a stable latency signal in a high-speed semiconductor device. A CAS latency circuit(100) includes an internal read command signal generation unit(110), a latency control clock generation unit(120), and a latency signal generation unit(130). The internal read command signal generation unit generates an internal read command signal(PREAD) in response to a read command. The latency control clock generation unit generates a plurality of latency control clocks. The latency signal generation unit receives the internal read command signal and the latency control clocks and generates latency signals(LATENCY) by shifting the internal read command signal. |
