MEMORY DEVICE WITH SELECTIVE ERROR CORRECTION CODE

摘要

A memory device for selectively performing ECC operation is disclosed. The memory device comprises: a plurality of first memory cell blocks having first bit lines; a second memory cell block having second bit lines; and an ECC unit. The second memory cell block stores parity bits for recovering a fail cell of the first memory cell blocks. The ECC unit selectively performs ECC operation for bit lines of a fail cell or word lines of a fail cell, in response to a command or a control signal applied from the outside of the memory device. The ECC unit detects an error bit position using parity bits for a corresponding fail cell and corrects error bit data.