发明名称 |
Memory devices and methods for high random transaction rate |
摘要 |
A memory device can include a random access memory array configured to store data values; a plurality of bi-directional ports, configured to transfer data values into and out of the memory device on rising and falling transitions of at least one access clock signal; and at least one address bus configured to receive at least a portion of address values to random access locations on rising and falling transitions a timing clock signal having the same frequency as the access clock signal. |
申请公布号 |
US8630111(B2) |
申请公布日期 |
2014.01.14 |
申请号 |
US201313859669 |
申请日期 |
2013.04.09 |
申请人 |
CYPRESS SEMICONDUCTOR CORPORATION |
发明人 |
MAHESHWARI DINESH;BARBARA BRUCE;MARINO JOHN |
分类号 |
G11C11/00 |
主分类号 |
G11C11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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