发明名称 |
Interconnection method and device, for example for systems-on-chip |
摘要 |
Transactions of the request/response type between a first circuit module and a second circuit module operating with incompatible protocols or interfaces envisage organizing a queue of memory locations for storing transaction information items and transaction identifiers associated to said transactions and implementing the transactions via operations of reading/writing of the locations in the queue, mapping on the transaction identifiers information for management of the queue. |
申请公布号 |
US8631184(B2) |
申请公布日期 |
2014.01.14 |
申请号 |
US201113112802 |
申请日期 |
2011.05.20 |
申请人 |
MANGANO DANIELE;URZI' IGNAZIO ANTONIO;STMICROELECTRONICS (GRENOBLE 2) SAS;STMICROELECTRONICS S.R.L. |
发明人 |
MANGANO DANIELE;URZI' IGNAZIO ANTONIO |
分类号 |
G06F13/20;G06F13/36;G06F13/40 |
主分类号 |
G06F13/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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