发明名称 Methods of forming integrated circuit chips having vertically extended through-substrate vias therein
摘要 Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.
申请公布号 US8629059(B2) 申请公布日期 2014.01.14
申请号 US20100969977 申请日期 2010.12.16
申请人 LEE HO-JIN;LEE KANG-WOOK;PARK MYEONG-SOON;CHOI JU-IL;HWANG SON-KWAN;SAMSUNG ELECTRONICS CO., LTD. 发明人 LEE HO-JIN;LEE KANG-WOOK;PARK MYEONG-SOON;CHOI JU-IL;HWANG SON-KWAN
分类号 H01L23/48 主分类号 H01L23/48
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