发明名称 |
Memory building blocks and memory design using automatic design tools |
摘要 |
The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis. |
申请公布号 |
US8631365(B2) |
申请公布日期 |
2014.01.14 |
申请号 |
US201213461571 |
申请日期 |
2012.05.01 |
申请人 |
KENGERI SUBRAMANI;CHOU CHUNG-CHENG;UPPUTURI BHARATH;CHENG HANK;KUO MING-ZHANG;CHEN PEY-HUEY;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
KENGERI SUBRAMANI;CHOU CHUNG-CHENG;UPPUTURI BHARATH;CHENG HANK;KUO MING-ZHANG;CHEN PEY-HUEY |
分类号 |
G06F9/45 |
主分类号 |
G06F9/45 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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