发明名称 |
Clock frequency divider circuit, clock distribution circuit, clock frequency division method, and clock distribution method |
摘要 |
To provide a clock frequency divider circuit that generates a clock signal enabling an expected proper communication in communication with a circuit operating by a clock having a different frequency. A clock frequency division circuit according to the present invention generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S by subtracting (S-N) clock pulses from S clock pulses of the input clock signal based on a frequency division ratio defined as N/S. The clock frequency division circuit generates a control signal used to preferentially subtract a clock pulse at a timing other than a communication timing of data communication performed by a target circuit using the output clock signal among S clock pulses of the input clock signal. Further, it generates the output clock signal by subtracting a clock pulse of the input clock signal according to the generated control signal. |
申请公布号 |
US8629703(B2) |
申请公布日期 |
2014.01.14 |
申请号 |
US201313798711 |
申请日期 |
2013.03.13 |
申请人 |
SHIBAYAMA ATSUFUMI;NEC CORPORATION |
发明人 |
SHIBAYAMA ATSUFUMI |
分类号 |
H03K3/00 |
主分类号 |
H03K3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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