发明名称 Memory control circuit, control method therefor, and image processing apparatus
摘要 In one embodiment, a circuit includes an input buffer, an output buffer, a counter, an issuing unit, a first controller, a register, and a second controller. The input buffer and the output buffer have a variable storage capacity. The counter cyclically counts from a first value to a second value. The issuing unit issues a write command if a count value of the counter is a third value and issues a read command if the count value is a fourth value. The register stores a first setting value, a second setting value and a third setting value to be capable of changing each of the setting values. The second controller controls the components to set the storage capacity, the second value, and one of the third and fourth values respectively to values corresponding to the first to third setting values.
申请公布号 US8631214(B2) 申请公布日期 2014.01.14
申请号 US201113287865 申请日期 2011.11.02
申请人 SATO HIROKI;KABUSHIKI KAISHA TOSHIBA;TOSHIBA TEC KABUSHIKI KAISHA 发明人 SATO HIROKI
分类号 G06F12/00 主分类号 G06F12/00
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