发明名称 Cell architecture for increasing transistor size
摘要 A cell-based architecture for an integrated circuit that uses at least two categories of cells: cut-gate cells and breaker cells. Cut-gate cells have gates that extend from one boundary of the cell to an opposite boundary of the cell. Cut gate features are located along the boundaries of the cell to indicate locations for cutting the gates during fabrication. Instances of the cut-gate cells are arranged in abutting rows that result in the formation of continuous gate strips during the fabrication process, which are then cut into individual gates with a cut-gate mechanism. Breaker cells have gates that do not extend to the boundaries of the breaker cell. To prevent the continuous gate strips from exceeding design rule requirements, instances of breaker cells are placed at intervals between the rows of cut-gate cell instances to restrict the size of the gate strips.
申请公布号 US8631374(B2) 申请公布日期 2014.01.14
申请号 US201213372311 申请日期 2012.02.13
申请人 SHERLEKAR DEEPAK D.;SYNOPSYS, INC. 发明人 SHERLEKAR DEEPAK D.
分类号 G06F17/50 主分类号 G06F17/50
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