| 摘要 |
Matrix memories comprising row conductors and column conductors, at the intersections of which storage elements are arranged, are often tested by complete addressing of all elements. Different bit patterns are written into the memory and tested upon reading. However, when the elements arranged at the intersections are EEPROM storage cells, requiring a substantial amount of time for writing, the complete testing of the memory in this manner would be very time consuming. In accordance with the invention, therefore, only the addressing of the matrix is tested, use being made of a special test bus which can be connected to the row conductors and the column conductors via switches. As a result, not only the row conductors and column conductors themselves, but also the associated decoders and selection elements can be tested for correct operation. This principle can be applied also in the case of memories consisting of several parallel matrices, for example for memories with multibit data words, and for memories in which the matrices are subdivided into a plurality of sub-matrices. |
