发明名称 |
Memory system with calibrated data communication |
摘要 |
An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values. |
申请公布号 |
US8630317(B2) |
申请公布日期 |
2014.01.14 |
申请号 |
US201213447080 |
申请日期 |
2012.04.13 |
申请人 |
ZERBE JARED LEVAN;DONNELLY KEVIN S.;SIDIROPOULOS STEFANOS;STARK DONALD C.;HOROWITZ MARK A.;YU LEUNG;VU ROXANNE;KIM JUN;GARLEPP BRUNO W.;HO TSYR-CHYANG;LAU BENEDICT CHUNG-KWONG;RAMBUS INC. |
发明人 |
ZERBE JARED LEVAN;DONNELLY KEVIN S.;SIDIROPOULOS STEFANOS;STARK DONALD C.;HOROWITZ MARK A.;YU LEUNG;VU ROXANNE;KIM JUN;GARLEPP BRUNO W.;HO TSYR-CHYANG;LAU BENEDICT CHUNG-KWONG |
分类号 |
H04J3/06;G06F1/10;G06F1/12;G06F13/42 |
主分类号 |
H04J3/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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